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Stratix II EP2S180 DSP Development Board Reference Manual
101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com
Development Board Version: 1.0.0 Document Version: 1.0.0 Document Date: August 2005
Copyright (c) 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Part Number MNL-S20705-1.0 Development Board Version 1.0.0 Stratix II EP2S180 DSP Development Board Reference Manual Preliminary Altera Corporation August 2005
Contents
About This Manual
How to Contact Altera .............................................................................................................................. v Typographic Conventions ........................................................................................................................ v
Chapter 1. Introduction
General Description ............................................................................................................................... Stratix II EP2S180 DSP Devlopment Board ................................................................................................................................ Components ...................................................................................................................................... Debugging Interfaces ....................................................................................................................... Expansion Interfaces ........................................................................................................................ Handling the Board ............................................................................................................................... 1-1 1-1 1-1 1-2 1-2 1-2
Chapter 2. Board Components & Interfaces
Components & Interfaces ..................................................................................................................... 2-1 Environmental Requirements ......................................................................................................... 2-3 Using the Board ..................................................................................................................................... 2-4 Apply Power ..................................................................................................................................... 2-4 Configure the Stratix II Device Directly ........................................................................................ 2-5 Nonvolatile Configuration ................................................................................................................... 2-5 Factory & User Configurations ...................................................................................................... 2-5 The Factory Design .......................................................................................................................... 2-7 Functional Description .......................................................................................................................... 2-8 Power ................................................................................................................................................. 2-8 Clocks & Clock Distribution ........................................................................................................... 2-9 Board Components .............................................................................................................................. 2-12 Stratix II Device (U18) .................................................................................................................... 2-12 Switch Inputs .................................................................................................................................. 2-13 Configuration Status LEDs ........................................................................................................... 2-14 Dual 7-Segment Display & LEDs ................................................................................................. 2-14 A/D Converters .............................................................................................................................. 2-16 D/A Converters .............................................................................................................................. 2-19 SRAM Memory (U43 & U44) ........................................................................................................ 2-22 Flash Memory (U17) ...................................................................................................................... 2-25 SDRAM Memory (U39 and U40) ................................................................................................. 2-27 Ethernet MAC/PHY (U16) ........................................................................................................... 2-31 CompactFlash Connector (CON1) ............................................................................................... 2-33 Mictor Connector (J20) ................................................................................................................... 2-36 VGA Interface (J35) ........................................................................................................................ 2-38 Audio CODEC (U5) ....................................................................................................................... 2-40
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Contents
Expansion Interfaces ........................................................................................................................... TI-EVM/FPDP Connector (J31, J33) ............................................................................................ RS-232C Serial I/O Interface ......................................................................................................... Analog Devices Corporation External A/D Support ............................................................... Expansion Prototype Connector (J23, J24, J25) ........................................................................... Expansion Prototype Connector (J26, J27, J28) ...........................................................................
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About This Manual
This manual provides comprehensive information about the Altera(R) Stratix II EP2S180 Development Board.
How to Contact Altera
Information Type
Technical support
For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada
www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time)
All Other Locations
www.altera.com/mysupport/ +1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time www.altera.com literature@altera.com + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time ftp.altera.com
Product literature Altera literature services Non-technical customer service FTP site
www.altera.com literature@altera.com (800) 767-3753
ftp.altera.com
Typographic Conventions
Visual Cue
Bold Type with Initial Capital Letters bold type
This document uses the typographic conventions shown below.
Meaning
Command names, dialog box titles, check box options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.
Italic Type with Initial Capital Letters
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v Preliminary
Typographic Conventions
Stratix II EP2S180 Development Board Reference Manual
Visual Cue
Italic type
Meaning
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file.
Initial Capital Letters "Subheading Title"
Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
Courier type
1., 2., 3., and a., b., c., etc. v 1
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic.
*
c w
r f
vi Preliminary
Altera Corporation August 2005
1. Introduction
General Description
The Stratix II EP2S180 DSP development board provides a hardware platform that designers can use to develop DSP systems based on Stratix II devices. Combined with DSP intellectual property (IP) from Altera and partners in the Altera Megafunction Partners Program (AMPPSM), users can quickly develop powerful DSP systems. Altera's unique OpenCore(R) Plus technology allows users to evaluate MegaCore(R) functions in hardware prior to licensing them. DSP Builder, version 5.0.1 includes a library for the Stratix II EP2S180 DSP development board. This library allows algorithm development, simulation, and verification on the board, all from within the MathWorks MATLAB/Simulink system-level design tool. Additionally, the Stratix II DSP development board includes a Texas Instrument EVM (crossplatform) daughter card connector, which enables development and verification of FPGA co-processors for off loading and accelerating compute-bound algorithms from programmable DSP processors.
Stratix II EP2S180 DSP Devlopment Board
The Stratix(R) II EP2S180 DSP development board is included with the DSP Development Kit, Stratix II Professional Edition (ordering code DSPDEVKIT-2S180). This board is a development platform for high-performance digital signal processing (DSP) designs, and features the Stratix II EP2S180 device in a 1020-pin package.
Components
Analog I/O Two 12-bit 125-MHz A/D converters Two 14-bit 165-MHz D/A converters One 8-bit, 180 megapixels-per-second triple D/A converter for VGA output One 96-KHz Stereo Audio coder/decoder (CODEC) Memory subsystem 1 MByte of 10-ns asynchronous SRAM configured as a 32-bit bus 16 MBytes of flash memory configured as an 8-bit bus 32 MBytes of SDRAM memory configured as a 64-bit bus CompactFlash connector supporting ATA and IDE access modes Configuration options On-board configuration using 16 MBytes of flash memory and an Altera(R) EPM7256 MAX(R) device
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Handling the Board

Download configuration data using an USB BlasterTM download cable Single-ended or differential inputs and outputs accessed via a Mictor connector Dual 7-segment display Four user-defined push-button switches One female 9-pin RS-232 connector 10/100 Ethernet MAC/PHY Eight user-defined LEDs Socketed 100-MHz oscillator Single 16-V DC power supply (adapter included) Active heat sink
Debugging Interfaces

One Mictor-type connector for Agilent and Tektronix logic analyzers Several 0.1-inch headers
Expansion Interfaces

Two connectors for Analog Devices A/D converter daughter cards Connector for Texas Instruments Evaluation Module (TI-EVM) daughter cards Two Expansion Prototype connectors
Handling the Board
When handling the board, it is important to observe the following precaution: w Static discharge precaution--Without proper anti-static handling the board can be damaged. Therefore, take anti-static precautions while handling the board.
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2. Board Components & Interfaces
Components & Interfaces
This chapter describes the operational and connectivity information for this board's major components and interface. Figure 2-1 shows a top view of the board components and interfaces.
Figure 2-1. Stratix II EP2S180 DSP Development Board Components nterfaces
Note to Figure 2-1:
(1) A TI-EVM/FPDP connector (J31, J33) is found on the reverse side of the board.
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Components & Interfaces
Table 2-1 describes the components on the board and the interfaces it supports.
Table 2-1. Stratix II EP2S180 DSP Development Board Components & Interfaces (Part 1 of 2) Component/ Interface Components
Stratix II device MAX Device A/D converters D/A converters 1 MByte SRAM 16 MBytes of flash memory 32 MBytes of SDRAM SMA external clock input connectors Dual 7-segment display Push-button switches User-defined LEDs Power-on LED CONF_DONE LED RS-232 connector FPGA PLD I/O I/O Memory Memory Memory Input Display I/O Display Display Display I/O U18 U10 U1, U2 U14, U15 U43, U44 U17 U39, U40 J10, J11, J12 U12, U13 SW4, SW5, SW6, SW7 D1 - D8 LED7 LED5 J29 EP2S180 Stratix II device
Type
Board Designation
Description
EPM7256ETC144 device
Two 12-bit 125-MHz A/D converters Two 14-bit 165-MHz D/A converters 1 MByte of 10-ns asynchronous SRAM configured as a 32-bit bus. 16 Mbytes of flash memory configured as an 8-bit bus. 32 MBytes of SDRAM memory configured as a 64-bit bus SMA connectors for inputs of external clock signals, terminated in 50 . Dual 7-segment display. Four push-button switches, which are user-defined as logic inputs. Eight user-defined LEDs. LED that illuminates when power is supplied to the board. LED that illuminates upon successful configuration of the Stratix II device. DB9 connector, configured as a DTE serial port. The interface voltages are converted to 3.3-V signals and brought to the Stratix II device, which must be configured to generate and accept transmissions. Socketed on-board 100-MHz oscillator. Board adapter for included 16-V DC power supply JTAG Connector used to configure the Stratix II device directly JTAG connector used to configure the configuration controller
100-MHz oscillator Single 16-V DC power supply
Clock Input
Y1 J22 (adapter) J21
Stratix II device Joint I/O Test Action Group (JTAG) Connector Configuration controller JTAG Connector I/O
J13
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Board Components & Interfaces
Table 2-1. Stratix II EP2S180 DSP Development Board Components & Interfaces (Part 2 of 2) Component/ Interface
VGA D/A Converter Audio CODEC CompactFlash card connector I/O I/O I/O
Type
Board Designation
U45 U5 CON1
Description
One 8-bit, 180 megapixels-per-second triple D/A converter for VGA output 96-KHz stereo audio CODEC CompactFlash card connector
Debugging Interfaces
Mictor connectors I/O J20 One Mictor header connected to 33 pins on the Stratix II device (32 data signals, 1 clock signal) for use with an external logic analyzer.
Expansion Interfaces
Analog Devices connector (1) TI-EVM connectors Expansion Expansion J5, J6 J31, J33 J23 - J25, J26 - J28 Interface to Analog Device's A/D converters via two 40-pin connectors. Interface to the TI-EVM. (The connectors are on the reverse side of the board.) The board provides two custom interfaces to daughter cards via 74-pin headers. (These pins can also be used for general I/O.) These connectors are referred to on the board as "Santa Cruz Daughter Card 1" and "Santa Cruz Daughter Card 2" Note to Table 2-1:
(1) These headers can be used to interface to Analog Devices A/D converter evaluation boards. They are designated as J5 and J6, and interface to Analog Devices AD6645/9433/9430 external A/D converters.
Expansion Prototype Expansion Connectors
Environmental Requirements
The Stratix II EP2S180 DSP development board must be stored between -40 C and 100 C. The recommended operating temperature is between 0 C and 55 C. w The Stratix II EP2S180 DSP development board can be damaged without proper anti-static handling.
f
The DSP Development Kit, Stratix II Professional Edition includes a heat sink and fan combination, also known as an active heat sink. Depending on the specific requirements of your application, this level of cooling may not be necessary.
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Using the Board
Using the Board
When power is applied to the board and SW9 is in the "ON" position, the Power-on LED (LED7) illuminates. At that time, the MAX device (U10) programs the Stratix II device (U18) from one of 4 flash memory spaces reserved for configuration information. If configuration is successful, the CONF_DONE LED (LED5) illuminates. 1 If the Stratix II device is programmed with a design in one of the user configuration memory spaces or using the JTAG connector (J21), both the CONF_DONE LED (LED5) and the USER LED (LED1) illuminate. For more information, refer to "Configuration Status LEDs" on page 2-14.
To configure the board with a new design, the designer should perform the following steps, explained in detail in this section. 3. 4. Apply power to the board. Reconfigure the Stratix II device.
Apply Power
Apply power to the board by connecting the 16-V DC power supply adapter in the DSP Development Kit, Stratix II Professional Edition to the on-board power adapter connector (J22), and then switch SW9 to the ON position. All of the board components draw power either directly from this 16-V supply or from the 3.3-V, 1.2-V, and 5-V regulators that are powered by the 16-V supply. 1 The 3.3-V supply provides VCCIO to the Stratix II device and all LVTTL board components. The 1.2-V supply provides VCCINT to the Stratix II device.
When power is applied to the board, the Power On LED (LED7) illuminates. c The Stratix II EP2S180 device, the A/D and D/A converters, and power regulator U22 become hot as the board is used. Because their surface temperature may significantly increase, do not touch these devices while power is applied to the board.
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Board Components & Interfaces
Configure the Stratix II Device Directly
You can configure the Stratix II device directly, without turning off power, using the Quartus(R) II software and the USB Blaster cable, as follows. 1. 2. Attach the cable to J21, also labeled "JTAG Stratix II". Open a Quartus II SRAM Object File (.sof), which starts the Quartus II Programmer. Select USB Blaster as the hardware. Set the mode to JTAG. Click Start.
3. 4. 5.
After successful configuration, the CONF_DONE LED (LED5) illuminates.
f Nonvolatile Configuration
Refer to Quartus II Help for instructions on how to use the USB Blaster cable. The designer must reconfigure the Stratix II device each time power is applied to the Stratix II DSP development board. For designers who want to power up the board and have a design immediately present in the Stratix II device, the board has a nonvolatile configuration scheme. This scheme consists of flash memory and a configuration controller (U10), which is an Altera EPM7256 PLD. The configuration controller device is non-volatile (i.e., it does not lose its configuration data when the board is powered down) and it comes factory-programmed with logic that configures the Stratix II EP2S180F1020C3 device (U18) from data stored in flash (U17) on power-up. Upon power-up, the configuration controller begins reading data from the flash memory. The flash memory, Stratix II device, and configuration controller are connected so that data from the flash configures the Stratix II device in fast passive-parallel mode.
Factory & User Configurations
The configuration controller can manage two separate Stratix II device configurations stored in flash memory: one user design and a factory design. On power-up, the configuration controller reads one of two (user or factory) designs from the flash memory and programs the Stratix II device accordingly. The user can select with which design the Stratix II device is programmed by setting the DIP switches on SW2.
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Nonvolatile Configuration
DIP switches 1 through 3 on SW2 select one of four possible Stratix II configuration images upon power-up. When DIP switch 4 is in the "OPEN" position the configuration controller is enabled. If DIP switch 4 is in the "OPEN" position and there are no valid user-defined images, the Stratix II device is programmed with the factory configuration. Table 2-2 shows the DIP switch combinations used to select the available images. See "Nonvolatile Configuration" on page 2-5 for more details. 1 Switch 4 of the SW2 DIP switch must be set to "OPEN" to enable the configuration controller.
Table 2-2. Configuration DIP Switch (SW2) Combinations Image
User0 Factory
Switch 1
Closed Open
Switch 2
Closed Open
Switch 3
Closed Open
Switch 4
Open Open
1
An alternative method of configuring the device with the factory design is to press push-button switch SW3.
You can load a customized user design or reload a factory design into the on-board flash memory by using the Nios II Flash Programmer in the Nios II SDK Shell.
Programming Example for the 2S180 DSP Development Board
The following example instructions illustrate how to program the 2S180 DSP Development Board. 1. Generate a flash file to load into the flash device. a. b. c. Run the NIOS II SDK Shell. Change directories to the project location. Run the sof2flash utility:
$ sof2flash --input=.sof -output=.flash --offset=0x00900000 You can use the offset switch to specify which configuration area of the flash will be loaded. Use 0x00900000 for User0 area, or 0x00200000 to overwrite the Factory. 2. Copy the flash file into the on-board flash device.
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Board Components & Interfaces
Move a copy of the flash programming SOF file to your project directory. The flash programming SOF file is in the location: <2S60_DevKit_Install_Directory>\Examples\HW\NiosII \altera_dsp_dev_board_stratix_2s180 \altera_dsp_dev_board_stratix_2s180.sof
3.
Run the Nios II Flash Programmer (nios2-flash-programmer) utility:
$ nios2-flash-programmer --base=0x01000000 --input=.flash --sof=altera_dsp_dev_board_stratix_2s180.sof --device=1
f
For more information on programming the flash memory or loading SOF files into the on-board flash memory, refer to the Nios II Flash Programmer User Guide.
The Factory Design
When the Stratix II device is programmed with the factory design, LEDs D5 through D8 behave as a binary counter that counts down to zero. This is a power-up indication that the board is functional and the device was successfully programmed with the factory design. Along with the LED counter, the factory design includes two blocks of IP generated by the Altera NCO Compiler. One of these oscillators is running at 10 times the frequency of the other, but both of them have the same amplitude, covering 13 bits of dynamic range. Two sine waves generated by these blocks are added together and the output is converted from a 2's complement representation into unsigned integer format. This combined sine wave signal with 14-bit dynamic range is sent to a 14-bit D/A converter. When the analog output of the D/A converter is connected, via the included SMA cable, with the analog input of one of the 12-bit A/D converters, the A/D converter's digital output is looped back to the Stratix II device. The design converts this loopback input from 2's complement format to unsigned integer format. The converted loopback data is captured by an instance of the SignalTap(R) II logic analyzer in the design for display and analysis.
f
For step-by-step instructions on how to use the factory design to test the functionality of the board, refer to the DSP Development Kit, Stratix II Professional Edition Getting Started User Guide.
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Functional Description
Functional Description
This section describes the elements of the Stratix II EP2S180 DSP development board. Figure 2-2 shows a block diagram of the board. Figure 2-2. Stratix II EP2S180 Development Board Block Diagram
A/D Converter A/D Converter 12 256K x 36 SRAM
12
256K x 36 SRAM
Mictor Connector D/A Converter D/A Converter 14 Stratix II EP2S180 Device Analog Devices A/D Converters Connector Prototyping Area Dual Seven-Segment Display TI-EVM Connector 0.1-inch Digital I/O Headers
14
80-MHz Oscillator JTAG Connector
RS-232
LEDs Configuration Controller 32 Mbit Flash 5.0 V SMA External Clock Input SMA External Clock Output Regulators Vccint (1.5 V) Vccio (3.3-V)
DIP Switches
Pushbutton Switches
Power
The 16-layer development board has 10 signal layers and 6 ground/VCC planes. The board is powered from a single, well regulated 16-V supply. Regulators on the board are used to develop the VCCINT (1.2 V), VCCIO (3.3 V), and VCC5 (5.0 V) voltages. The board includes a Power-on LED that indicates the presence of VCCIO. The following board elements are powered by the 3.3 V supply:

LEDs Switches Crystal oscillator
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Board Components & Interfaces
Table 2-3 lists the reference information for the 16-V power supply, which connects from the wall socket to the DSP development board.
Table 2-3. Power Supply Specifications Item
Board reference Part number Device description Description N/A (power supply adapter) TR9KT3750LCP-Y Switching power supply, Input: 100-240 V, ~1.2 A max., 50-60 Hz Output: +16 V, 3.75 A, 60 W max. GlobTek Inc. www.globtek.com
Manufacturer Manufacturer web site
Clocks & Clock Distribution
Table 2-4 lists the clocks and their signal distribution throughout the board.
Table 2-4. Clock Distribution Signals (Part 1 of 2) Signal Name
dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n sdram_CLK adc_PLLCLK1 adc_PLLCLK2 audio_CLK pld_MICTORCLK pld_CLKOUT
Comes From
Stratix II device pin B15 (PLL5_OUT0p) Stratix II device pin C15 (PLL5_OUT0n) Stratix II device pin C16 (PLL5_OUT1p) Stratix II device pin D16 (PLL5_OUT1n)
Goes To
DAC A (U14 pin 28) DAC A (U14 pin 28) DAC B (U15 pin 28) (2) DAC B (U15 pin 28) (2)
Stratix II device pin AK16 SDRAM (U39 U40 pins 68) (PLL6_OUT0p) Stratix II device pin B18 (PLL11_OUT0p) Stratix II device pin D18(PLL11_OUT0n) Stratix II device pin AL18(PLL12_OUT0p) Stratix II device pin M25 Stratix II device pin J14 ADC A (U1 pins 8, 7) (1) ADC B (U2 pins 8, 7) (1) Audio CODEC (U5 pin 25) Mictor Connector (J20 pin 5) PROTO1 (J25 pin 11) and PROTO2 (J28 pin 11) via a buffer (U7)
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Functional Description
Table 2-4. Clock Distribution Signals (Part 2 of 2) Signal Name
pld_CLKIN0,pld_CLK IN1 pld_CLKIN0_n,pld_C LKIN1_n proto1_OSC, proto2_OSC cpld_CLKOSC adc_CLK_IN1, adc_CLK_IN2 dac_CLKIN1, dac_CLKIN2 pld_CLKFB adc_CLK_IN1_n, adc_CLK_IN2_n dac_DACCLKIN1, dac_DACCLKIN2 pld_DACCLKIN proto1_CLKOUT, proto2_CLKOUT Notes to Table 2-4:
(1) (2) J3 and J4 control which clock is routed to the A/D converters. See Table 2-10 for details. J18 and J19 control which clock is routed to the D/A converters. See Table 2-16 for details.
Comes From
100-MHz oscillator External CLKIN_n input (J11) 100-MHz oscillator
Goes To
Stratix II device pins AM17 and A16 Stratix II device pins AL17 and B16 PROTO1 (J25 pin 9) and PROTO2 (J28 pin 9) via a buffer (U7) CPLD (U10 pin 125) ADC A (U1 pins 8, 7) and B (U2 pins 8, 7) (1) DAC A (U14 pin 28) and B (U15 pin 28) (2)
100-MHz oscillator 100-MHz oscillator 100-MHz oscillator
pld_CLKOUT signal from Stratix II device pin U1 the Stratix II pin J14 External CLKIN_n input (J11) External DA_EXT_CLK input (J12) External DA_EXT_CLK input (J12) ADC A (U1 pins 8, 7) and B (U2 pins 8, 7) (1) DAC A (U14 pin 28) and B (U15 pin 28) (2) Stratix II device pin E16
Stratix II device pins T32 and PROTO1 (J25 pin 13) PROTO2 (J28 pin 13) via T30 a buffer (U7)
The Stratix II EP2S180 DSP development board can obtain a clock source from one or more of the following sources:

The on-board crystal oscillator An external clock (through an SMA connector or a Stratix II pin)
The board can provide independent clocks from both the enhanced and fast PLLs to the A/D converters, the D/A converters, and the other components that require stable clock sources. To implement this concept, the enhanced PLL5-dedicated pins drive the A/D converters and associated functions, and the enhanced PLL6-dedicated pins drive the D/A converters and associated functions.
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Board Components & Interfaces
Figure 2-3 shows each clock and its distribution throughout the board. Figure 2-3. Clock Distribution
100-MHz Oscillator Configuration Controller Expansion Prototype Connector
Clock Distribution 1
Clock Distribution 2
Expansion Prototype Connector
CLK_IN_p
SDRAM
Stratix II EP2S180F1020C3 Device
Audio CODEC
CLK_IN_n Clock Distribution 3
ADC A Jumper
CLK Buffer
ADC A
ADC B Jumper DA_EXT_CLK Clock Distribution 4 DAC A Jumper
CLK Buffer
ADC B
DAC
DAC B Jumper
DAC
Table 2-5 lists reference information for the 100-MHz socketed oscillator.
Table 2-5. 100-MHz Socketed Oscillator Reference Item
Board reference Part number Device description Manufacturer Manufacturer web site Y1 ECS-UPO-8PIN 100MHz Oscillator ECS Inc. www.ecsxtal.com
Description
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Board Components
1
Clock Distribution 1 source can be either the oscillator (Y1) or an external clock inserted using J10. To use an external clock signal, remove the crystal oscillator from its socket. Note the correct orientation of the oscillator before removing it to ensure you reinstall it correctly for future use.
Board Components
The following sections describe the development board components.
Stratix II Device (U18)
The Stratix II EP2S180 device on the board features 71,760, adaptive logic modules (ALMs) in a (-3) speed grade 1020-pin FineLine BGA(R) package. The device has 9,383,040 total RAM bits.
f
For more information on Stratix II devices, refer to the Stratix II Device Handbook.
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Board Components & Interfaces
Table 2-6 describes the features of the Stratix II EP2S180F1020C3 device.
Table 2-6. Stratix II EP2S180 Features Feature
ALMs Adaptive look-up tables (ALUTs) (1) Equivalent LEs (2) M512 RAM blocks M4K RAM blocks M-RAM blocks Total RAM bits DSP blocks 18-bit x 18-bit multipliers (3) Enhanced PLLs Fast PLLs Maximum user I/O pins Package type Board reference Voltage Notes to Table 2-6:
(1) (2) (3) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus II software for logic synthesis. This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture). These multipliers are implemented using the DSP blocks.
71,760 143,520 179,400 930 768 9 9,383,040 96 384 4 8 742 1020-pin FineLine BGA U15 1.2-V internal, 3.3-V I/O
Switch Inputs
The board has four push-button switches for user-defined logic input. Each push-button signal, when pressed drives logic low, and when released resumes driving logic high.
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Table 2-7 shows the pin-outs for the push-button switches.
Table 2-7. Push-button Switch PinOuts Signal Name
SW4 SW5 SW6 SW7
Stratix II Pin
K14 J15 L13 J13
Configuration Status LEDs
The configuration controller is connected to four status LEDs that show the configuration status of the board at a glance. By looking at the LEDs, you can determine which configuration, if any, was loaded into the FPGA at power-on. If a new configuration is downloaded into the Stratix II device via the JTAG interface, then the USER LED (LED1) remains illuminated. The rest of the configuration status LEDs turn off if the unused pins are configured as inputs, tri-stated for the Stratix II device. Table 2-8 shows the behavior of the configuration status LEDs.
Table 2-8. Configuration Status LED Indicators LED
LED3 LED4
LED Name
Loading Error
Color
Green Red
Description
This LED blinks while the configuration controller is actively transferring data from flash memory into the Stratix II FPGA. If the red Error LED is illuminated, then configuration was not transferred from flash memory into the Stratix II device. This can happen, if the flash memory contains neither a valid user or factory configuration. This LED illuminates when the user configuration is being transferred from flash memory and stays illuminated when the user configuration data is successfully loaded into the Stratix II device. This LED illuminates when the factory configuration is being transferred from flash memory and stays illuminated if the factory configuration was successfully loaded into the Stratix II device.
LED1
User
Green
LED2
Factory
Amber
Dual 7-Segment Display & LEDs
A dual 7-segment display and two LEDs is provided. The segments illuminate if the Stratix II pin to which they are connected drives low. The segemnts are not illuminated when the connected Stratix II device pin
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drives high. Conversely, the LEDs illuminate if the connected Stratix II device pin drives high, and are not illuminated when the connected Stratix II device pin drives low. Table 2-9 shows the pin-outs for the 7-segment display and LEDs.
Table 2-9. 7-Segment Display & LED Pin-Outs Signal Dual 7-Segment Display
HEX_0A HEX_0B HEX_0C HEX_0D HEX_0E HEX_0F HEX_0G HEX_0DP HEX_1A HEX_1B HEX_1C HEX_1D HEX_1E HEX_1F HEX_1G HEX_1DP C4 C5 B5 B6 D7 C7 B8 B9 F9 E9 C10 C11 F11 F12 C12 B12
Stratix II Pin
LEDs
pld_LED0 (board designation: D1) pld_LED1 (board designation: D2) pld_LED2 (board designation: D3) pld_LED3 (board designation: D4) pld_LED4 (board designation: D5) pld_LED5 (board designation: D6) pld_LED6 (board designation: D7) pld_LED7 (board designation: D8) B4 D5 E5 A4 A5 D6 C6 A6
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Figure 2-4 shows the pin-outs for the 7-segment display. Figure 2-4. Pin-Out Diagram for the Dual 7-Segment Display
HEX_0A HEX_0F HEX_0B HEX_1F HEX_1A HEX_1B
HEX_1G
HEX_0G
HEX_0D
HEX_0C
HEX_0E
HEX_0DP
HEX_1D
HEX_1C HEX_1DP Altera Corporation
A/D Converters
The Stratix II EP2S180 DSP development board has two 12-bit A/D converters that produce samples at a maximum rate of 125 mega-samples per second (MSPS). The A/D subsystem of the board has the following features:

The data output format from each A/D converter to the Stratix II device is in two's complement format. The circuit has a wideband, AC-coupled, differential input useful for IF sampling. The analog inputs are transformer-coupled to the A/D converter to create a balanced input. To maximize performance, two transformers are used in series. The Analog Devices data sheet for the AD9433 device describes the detailed operation of this circuit. Any required anti-aliasing filtering can be installed externally. If needed, users can purchase in-line SMA filters from a variety of manufacturers, such as Mini-Circuits (www.minicircuits.com). The transformer-coupled AC circuit has a lower 3-dB frequency, of approximately 1 MHz.
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The clock signal that drives the A/D converters can originate from the Stratix II device, the external clock input, or the on-board 100-MHz oscillator. Jumper J3 controls which clock is used for ADC A and J4 is used
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to select the clock for ADC B. Table 2-10 explains how to select these three clock signals. The selected clock will pass through a differential LVPECL buffer before arriving at the clock input to both A/D converters
Table 2-10. A/D Clock Source Settings J3, J4 Setting
Pins 1 and 2 Pins 3 and 4 Pins 5 and 6
Clock Source
Stratix II PLL circuitry OSC or External input clock positive
Signal Name
adc_PLLCLK1, adc_PLLCLK2 adc_CLK_IN1, adc_CLK_IN2
OSC or External adc_CLK_IN1_n, input clock negative adc_CLK_IN2_n
Table 2-11 lists reference information for the A/D converters.
Table 2-11. A/D Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer web site U1, U2 AD9433BSQ 12-bit, 125-MSPS A/D converter 3.3-V digital VDD, 5.0-V analog VDD Analog Devices www.analog.com
Description
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A/D Converter Stratix II Pin-Outs
Tables 2-12 and 2-13 show the ADC A (U1) and ADC B (U2) Stratix II pin-outs.
Table 2-12. ADC A (U1) Stratix II PinOuts Signal Name
adcA_D0 (LSB) adcA_D1 adcA_D2 adcA_D3 adcA_D4 adcA_D5 adcA_D6 adcA_D7 adcA_D8 adcA_D9 adcA_D10 adcA_D11 (MSB)
Stratix II Pin
D1 D2 E3 E4 E1 E2 F3 F4 F1 F2 G3 G4
Table 2-13. ADC B (U2) Stratix II PinOuts Signal Name
adcB_D0 (LSB) adcB_D1 adcB_D2 adcB_D3 adcB_D4 adcB_D5 adcB_D6 adcB_D7 adcB_D8 adcB_D9 adcB_D10 adcB_D11 (MSB)
Stratix II Pin
G1 G2 J3 J4 H1 H2 J1 J2 K3 K4 K1 K2
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D/A Converters
The Stratix II EP2S180 DSP development board has two D/A converters. The D/A subsystem of the board has the following features:

The converters produce 14-bit samples at a maximum rate of 165 MSPS. The analog output from each D/A converter is single-ended. The D/A converters expect data in an unsigned integer format.
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The D/A clock signals are output directly from the Stratix II device to the converters. Figure 2-5 shows the on-board circuitry after a D/A converter. The output of a D/A converter chip, DAC904, consists of a current source whose maximum value is 20 mA. This differential output is converted to a single -ended output using an RF transformer. The DSP board uses a 1:1 ratio transformer to interface to a 50 ohm impedance load. Each of the outputs is terminated with a 49.9 ohm resistor to ground. This circuit results in outputs being AC-coupled and inherently isolated due to transformer's magnetic coupling. The output of the transformer is then brought to an SMA connector. Figure 2-5. On-Board Circuitry after D/A Converter
1
The development kit includes an SLP-50 anti-aliasing filter from Mini-Circuits. This filter provides a 55-MHz cut-off frequency. For systems with other bandwidth requirements, a variety of anti-aliasing filters are available from commercial manufacturers that suit system requirements.
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Table 2-14 shows the reference information for the anti-aliasing filter.
Table 2-14. Anti-Aliasing Filter Reference Item
Board reference Manufacturer Description Part number Manufacturer web site N/A Mini-circuits Anti-aliasing filter SLP-50 www.minicircuits.com
Description
Table 2-15 lists reference information for the D/A converters.
Table 2-15. D/A Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer web site
Description
U14, U15 DAC904 14-bit, 165-MSPS D/A converter 3.3-V digital VDD, 5.0-V analog VDD Texas Instruments www.ti.com
Table 2-16 lists the clock source settings for the D/A converters.
Table 2-16. D/A Clock Source Settings J18, J19 Setting
Pins 1 and 2 Pins 3 and 4 Pins 5 and 6 Pins 7 and 8
Clock Source
Stratix II PLL Circuitry Stratix II PLL Circuitry OSC or External input clock (J10) External input clock (J12) DA EXT CLK
Signal Name
dac_PLLCLK1, dac_PLLCLK2 dac_PLLCLK1_n, dac_PLLCLK2_n dac_CLK_IN1, dac_CLK_IN2 dac_DACCLKIN1, dac_DACCLKIN2
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D/A Converter Stratix II Pin-Outs
Tables 2-17 and 2-18 show the D/A A (U14) and D/A B (U15) Stratix II pin-outs.
Table 2-17. D/A A (U14, J15) Stratix II PinOuts Signal Name
dacA_D1 (MSB) dacA_D2 dacA_D3 dacA_D4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 (LSB)
Stratix II Pin
U5 U6 U10 U11 V9 V10 V6 V7 V4 V5 W8 W9 W6 W7
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Table 2-18. D/A B (U15, J17) Stratix II Pin-Outs Signal Name
dacB_D1 (MSB) (1) dacB_D2 dacB_D3 dacB_D4 dacB_D5 dacB_D6 dacB_D7 dacB_D8 dacB_D9 dacB_D10 dacB_D11 dacB_D12 dacB_D13 dacB_D14 (LSB) Note to Table 2-18:
(1) The Texas Instruments (TI) naming conventions differ from those of Altera Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the most significant bit (MSB) and bit 14 as the least significant bit (LSB).
Stratix II Pin
W4 W5 Y6 Y7 Y8 Y9 Y10 Y11 AB5 AB6 AA10 AA11 AA6 AA7
SRAM Memory (U43 & U44)
U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices. They are connected to the Stratix II device so they can be used by a Nios(R) II embedded processor as general-purpose memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. Refer to Table 2-19 for Stratix II device pin-outs for SRAM devices U43 and U44.
Table 2-19. SRAM Memory (U43 & U44) (Part 1 of 3) Pin Name
SE_A0 SE_A1 SE_A2 SE_A3 SE_A4
Pin Number
AD8 AM27 AM28 AJ27 AK27
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Table 2-19. SRAM Memory (U43 & U44) (Part 2 of 3) Pin Name
SE_A5 SE_A6 SE_A7 SE_A8 SE_A9 SE_A10 SE_A11 SE_A12 SE_A13 SE_A14 SE_A15 SE_A16 SE_A17 SE_A18 SE_A19 SE_D0 SE_D1 SE_D2 SE_D3 SE_D4 SE_D5 SE_D6 SE_D7 SE_D8 SE_D9 SE_D10 SE_D11 SE_D12 SE_D13 SE_D14 SE_D15 SE_D16 SE_D17
Pin Number
AL29 AM29 AJ28 AH28 AK20 AJ20 AL21 AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 AC21 AD21 AB21 AE21 AG20 AF21 AD22 AF22 AE22 AC17
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Table 2-19. SRAM Memory (U43 & U44) (Part 3 of 3) Pin Name
SE_D18 SE_D19 SE_D20 SE_D21 SE_D22 SE_D23 SE_D24 SE_D25 SE_D26 SE_D27 SE_D28 SE_D29 SE_D30 SE_D31 SRAM_BE_N0 SRAM_BE_N1 SRAM_BE_N2 SRAM_BE_N3 SRAM_CS_N SRAM_OE_N SRAM_WE_N
Pin Number
AE19 AD19 AC18 AB17 AC19 AL26 AL27 AL28 AK28 AK29 AC13 AD10 AC11 AE11 AG11 AK10 AK11 AL11 AL12 AG14 AH14
Table 2-20 lists the reference information for the SRAM memory.
Table 2-20. SRAM Memory Reference Item
Board reference Part Number Device description Manufacturer Manufacturer web site
Description
U43, U44 IDT71V416S10PH SRAM Memory IDT www.idt.com
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Flash Memory (U17)
U17 is a 16-Mbyte AMD AM29LV128M flash memory device connected to the Stratix II device. It can be used for two purposes:
A Nios II embedded processor implemented in the Stratix II device can use the flash as general-purpose readable memory and nonvolatile storage. The flash memory can hold a Stratix II device configuration file that is used by the configuration controller to load the Stratix II device at power-up.
Refer to Table 2-21 for Stratix II pin-outs for flash memory device U17. Hardware configuration data that implements the sines reference design is prestored in this flash memory and configures the Stratix II device with this design on boot up. A Nios II reference design can identify the 16Mbyte flash memory in its address space, and can program new data (either new Stratix II configuration data, Nios II embedded processor software, or both) into flash memory. For an example of programming the flash memory, refer to "Programming Example for the 2S180 DSP Development Board" on page 2-6.
Table 2-21. Flash Memory (U17) (Part 1 of 2) Pin Name
FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14
Pin Number
AF30 AF29 AE30 AE29 AG32 AG31 AF32 AF31 AE32 AE31 AD32 AD31 AB28 AB27 AC32
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Table 2-21. Flash Memory (U17) (Part 2 of 2) Pin Name
FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_CS_N FLASH_OE_N FLASH_RW_N flash_WP_n
Pin Number
AC31 AB30 AB29 Y29 Y28 AA30 AA29 AB32 AB31 AH30 AH29 AJ32 AJ31 AG30 AG29 AH32 AH31 AA32 AA31 W32 Y30
Table 2-22 lists the reference information for the flash memory.
Table 2-22. Flash Memory Reference Item
Board reference Part number Device description Manufacturer Manufacturer web site U17 AM29LV128MH103REI Flash Memory AMD www.amd.com
Description
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SDRAM Memory (U39 and U40)
The SDRAM devices (U39 and U40) are 2 Micron MT48LC4M32B2 devices with PC100 functionality and self refresh mode. The SDRAM is fully synchronous with all signals registered on the positive edge of the system clock. The SDRAM device pins are connected to the Stratix II device. An SDRAM controller peripheral is included with the Stratix II DSP Development Kit, Professional Edition, and allows a Nios II processor to view the SDRAM devices as a large, linearly-addressable memory. Table 2-23 lists the Stratix II device pin-outs for SDRAM device U39.
Table 2-23. SDRAM Device (U39) Pin-Outs (Part 1 of 2) Pin Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
Pin Number Connects to Stratix II Pin
25 26 27 60 61 62 63 64 65 66 24 21 22 23 2 4 5 7 8 10 11 13 74 AD11 AD13 AB13 AE14 AB14 AC14 AD14 AE10 AB15 AC16 AB16 AE13 AL9 AF11 AL4 AJ5 AH5 AM4 AG9 AH6 AH7 AH9 AM5
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Table 2-23. SDRAM Device (U39) Pin-Outs (Part 2 of 2) Pin Name
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CKE CS_N WE_N CLK
Pin Number Connects to Stratix II Pin
76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59 19 18 67 20 17 68 AK6 AJ6 AM6 AM7 AK7 AJ7 AM8 AJ10 AK8 AJ8 AM9 AF12 AG10 AF10 AG12 AJ11 AH11 AL10 AM10 AK12 AJ12 AM11 AM12 AK5 AG8 AH8 AL5 AK4 AL8 AL7 AL6 AK9 AK16
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Table 2-24 lists the Stratix II device pin-outs for SDRAM device U40.
Table 2-24. SDRAM Device (U40) Pin-Outs (Part 1 of 2) Pin Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17
Pin Number
25 26 27 60 61 62 63 64 65 66 24 21 22 23 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33
Connects to Stratix II Pin
AD11 AD13 AB13 AE14 AB14 AC14 AD14 AE10 AB15 AC16 AB16 AE13 AL9 AF11 AH13 AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AL20 AH19 AJ19 AH20 AM21 AK21 AJ21 AM22 AJ23 AK22
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Table 2-24. SDRAM Device (U40) Pin-Outs (Part 2 of 2) Pin Name
DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CKE CS_N
Pin Number
34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59 19 18 67 20
Connects to Stratix II Pin
AG22 AG23 AM23 AK23 AK24 AM24 AK25 AH24 AH26 AG24 AM26 AM25 AJ26 AK26 AK13 AL13 AB12 AC12 AK4 AL8 AL7 AL6
Table 2-25 lists the reference information for the SDRAM memory.
Table 2-25. SDRAM Memory Reference Item
Board reference Part number Device description Manufacturer Manufacturer web site
Description
U39, U40 MT48LC4M32B2TG-7 SDRAM Memory Micron www.micron.com
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Ethernet MAC/PHY (U16)
The LAN91C111 (U16) is a mixed signal analog/digital device that implements protocols at 10 Mbps and 100 Mbps. The control pins of U16 are connected to the Stratix II device so that user logic (e.g., the Nios II processor) can access Ethernet via the RJ-45 connector (RJ1). Refer to Table 2-26 for Stratix II pin-outs for Ethernet MAC/PHY device U16.t
Table 2-26. Ethernet MAC/PHY (U16) (Part 1 of 3) Pin Name
ENET_ADS_N ENET_AEN ENET_BE_N0 ENET_BE_N1 ENET_BE_N2 ENET_BE_N3 ENET_DATACS_N ENET_INTRQ0 ENET_IOCHRDY ENET_IOR_N ENET_IOW_N ENET_LDEV_N enet_RESET_n ENET_SRDY_N ENET_W_R_N SE_A0 SE_A1 SE_A2 SE_A3 SE_A4 SE_A5 SE_A6 SE_A7 SE_A8 SE_A9 SE_A10 SE_A11 T25 T21 AD8 AM27 AM28 AJ27 AK27 AL29 AM29 AJ28 AH28 AK20 AJ20 AL21
Pin Number
AA25 AC25 AE26 AE25 AD25 AD24 T20 AB23 V26 AC24 AB26 T26
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Table 2-26. Ethernet MAC/PHY (U16) (Part 2 of 3) Pin Name
SE_A12 SE_A13 SE_A14 SE_A15 SE_A16 SE_A17 SE_A18 SE_A19 SE_D0 SE_D1 SE_D2 SE_D3 SE_D4 SE_D5 SE_D6 SE_D7 SE_D8 SE_D9 SE_D10 SE_D11 SE_D12 SE_D13 SE_D14 SE_D15 SE_D16 SE_D17 SE_D18 SE_D19 SE_D20 SE_D21 SE_D22 SE_D23 SE_D24
Pin Number
AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 AC21 AD21 AB21 AE21 AG20 AF21 AD22 AF22 AE22 AC17 AE19 AD19 AC18 AB17 AC19 AL26 AL27
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Table 2-26. Ethernet MAC/PHY (U16) (Part 3 of 3) Pin Name
SE_D25 SE_D26 SE_D27 SE_D28 SE_D29 SE_D30 SE_D31
Pin Number
AL28 AK28 AK29 AC13 AD10 AC11 AE11
Table 2-27 lists the reference information for the Ethernet MAC/PHY.
Table 2-27. Ethernet MAC/PHY Reference Item
Board reference Part Number Device description Manufacturer Manufacturer web site U16 LAN91C111-NE Ethernet MAC/PHY SMSC www.smsc.com
Description
CompactFlash Connector (CON1)
The CompactFlash connector header (CON1) enables hardware designs to access a CompactFlash card. The following two access modes are supported:

ATA (hot-swappable mode) IDE (IDE hard-disk mode)
Most pins of CON1 connect to I/O pins on the FPGA. The following pins have special connections:
Pin 13 of CON1 (VCC) is driven by a power MOSFET that is controlled by an FPGA I/O pin. This allows the FPGA to control power to the CompactFlash card for the IDE connection mode. Pin 26 of CON1 (CD1#) is pulled up to 5V through a 10-K resistor. This signal is used to detect the presence of a CompactFlash card. When the card is not present, the signal is pulled high through the pull-up resistor.
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Pin 41 of CON1 (RESET) is pulled up to 5V through a 10-K resistor, and is controlled by the EPM7128AE configuration controller. The FPGA can cause the configuration controller to assert RESET, but the FPGA does not drive this signal directly.
Table 2-28 provides CompactFlash pin-out details.
Table 2-28. CompactFlash (CON1) Pin Table (Part 1 of 2) Pin on CompactFlash (CON1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CompactFlash Function (U60)
GND D03 D04 D05 D06 D07 CS0# A10 ATA_SEL# A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 DO0 DO1 DO2 IOCS16# CD2# CD1#
Connects to (1)
GND AA3 AA1 Y2 W1 V2 AE3 AF1 AD12 AF3 AF4 AG1 VCC (2) AD6 AD7 AA8 AA9 AE2 AD2 AE1 AB3 AB1 Y4 AD1 AB8 (3) AC15
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Table 2-28. CompactFlash (CON1) Pin Table (Part 2 of 2) Pin on CompactFlash (CON1)
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes to Table 2-28:
(1) (2) (3) (4) All pin numbers represent I/O pins on the FPGA, unless otherwise noted. This FPGA I/O pin controls a power MOSFET that supplies 5V VCC to CON1. This pin does not connect to the FPGA directly. RESET is driven by the EPM7256AE configuration controller device.
CompactFlash Function (U60)
D11 D12 D13 D14 D15 CS1# VS1# IORD# IOWR# WE# INTRQ VCC CSEL# VS2# RESET (4) WAIT# INPACK# REG# DASP# PDIAG# DO8 DO9 D10 VSS
Connects to (1)
AA2 AA4 Y5 AB2 AB4 AC9 AB10 AC2 AC1 AC6 AC4 VCC (2) AC8 AB9 AE12 AC3 AC7 AB7 AE4 AF2 V3 W2 Y3 GND (3)
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Table 2-29 lists the reference information for the CompactFlash connector.
Table 2-29. CompactFlash Connector Reference Item
Board reference Part Number Device description Manufacturer Manufacturer web site
Description
CON1 53856-5010 CompactFlash connector Molex www.molex.com
f
For general information on CompactFlash, see www.compactflash.org.
Mictor Connector (J20)
The Mictor connector (J20) can be used to transmit up to 27 high-speed I/O signals with very low noise via a shielded Mictor cable. J20 is used as a debug port. Twenty-five of the Mictor connector signals are used as data, and two signals are used as clock input and clock output. Most pins on J20 connect to I/O pins on the Stratix II device (U18). For systems that do not use the Mictor connector for debugging the Nios II processor, any on-chip signals can be routed to I/O pins and probed at J20 via a Mictor cable. External scopes and logic analyzers can connect to J20 and analyze a large number of signals simultaneously.
f
For details on Nios II debugging products that use the Mictor connector, see www.altera.com. Figure 2-6 shows an example of an in-target system analyzer ISA-Nios/T (sold separately) by First Silicon Solutions (FS2) Inc. connected to the Mictor connector. For details see www.fs2.com.
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Figure 2-6. An ISA-Nios/T Connecting to the Mictor Connector (J20)
J25
BUSY COMM RUN POWER
1
Five of the signals connect to both the JTAG pins on the Stratix II device (U18) and the Stratix II device's JTAG connector (J24). The JTAG signals have special usage requirements. You cannot use J20 and J24 at the same time. Figure 2-7 below shows connections from the Mictor connector to the Stratix II device. Figure 2-8 shows the pin-out for J20. Unless otherwise noted, labels indicate Stratix II device pin numbers. Figure 2-7. Mictor Connector Signaling
Mictor Connector (J20)
JTAG Connector
(J21)
Stratix II Device (U18)
5 40
Figure 2-8. Debug Mictor Connector - J20
P 35 27 P 33 26 P 31 29 P 29 28 N 27 27 N 25 26 N 23 25 N 21 24 TR 19 S TT 17 DI T 15 MS T 13 CK M 11 27 TD 9O M 2 76 N 23 5 N 2 32 N C 1 N C
Altera Corporation
37
38
C N 2 C N LK 4 _C TR 64 P2 8 25 P 3.3 10 CC V 3.3 12 C VC 14 26 R 16 27 R 18 22 R 20 23 R 22 24 R 24 25 R 26 28 R 28 29 R 30 27 T 32 28 T 34 22 T 36 23 T
Core Version a.b.c variable 2-37 Stratix II EP2S180 DSP Development Board Reference Manual
Board Components
Table 2-30 lists the reference information for the Mictor connector.
Table 2-30. Mictor Connector Reference Item
Board reference Part number Device description Manufacturer Manufacturer web site
Description
J20 2-767004-2 Mictor connector Tyco www.tyco.com
VGA Interface (J35)
The board contains a high density DP15 connector, which outputs VGA, as well as a Triple Video D/A converter which has the following features:

3 x 8 bit, 180 megapixels per second 2.5% gain matching 0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3-V power supply
Table 2-31 shows the pin-outs for the VGA interface.
Table 2-31. VGA Interface (U45, J35) Pin-Outs (Part 1 of 2) Signal
vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 vga_G0 vga_G1 vga_G2 vga_G3
Stratix II Pin
B7 E7 E6 A7 C9 A8 C8 A9 E11 G10 G11 G12
2-38 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Table 2-31. VGA Interface (U45, J35) Pin-Outs (Part 2 of 2) Signal
vga_G4 vga_G5 vga_G6 vga_G7 vga_R0 vga_R1 vga_R2 vga_R3 vga_R4 vga_R5 vga_R6 vga_R7 vga_BLANK_n vga_CLOCK vga_HSYNC vga_VSYNC vga_SYNC_n
Stratix II Pin
D12 A11 B11 A12 D8 E8 F8 F10 A10 B10 D10 D11 G13 E13 F15 B14 F13
Table 2-32 describes the device used to implement the VGA interface.
Table 2-32. VGA Interface Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer web site
Description
U45 FMS3818KRC Triple Video D/A Converter 3.3 V Fairchild www.fairchildsemi.com
Altera Corporation
Core Version a.b.c variable 2-39 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Audio CODEC (U5)
The board contains three stereo jack connectors, which serve as one stereo input, one amplified stereo output, and one non-amplified stereo output. The stereo jacks are driven by a Stereo Audio CODEC running at 8-96 KHz. Table 2-33 shows the pin-outs for the CODEC.
Table 2-33. Audio CODEC (U5) Pin-Outs Signal
audio_BCLK audio_CS_n audio_SDIN audio_SCLK audio_MODE audio_DOUT audio_DIN audio_LRCIN audio_LRCOUT audio_CLK
Stratix II Pin
AG4 AH1 AH2 AH3 AH4 AJ1 AJ2 AG2 AG3 AL18
Table 2-34 describes the device used to implement the CODEC.
Table 2-34. Audio CODEC Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer web site
Description
U5 TLV320AIC23PW Stereo Audio CODEC, 8-96 KHz 3.3 V Texas Instruments www.ti.com
Expansion Interfaces
The Stratix II EP2S180 DSP development board includes the following interfaces:

A TI-EVM/FPDP connector (J31, J33), located on the reverse side of the board An RS-232C Serial I/O interface (J29)
2-40 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Two 0.1-inch headers specifically designed to be used with external analog-to-digital devices made by Analog Devices Corporation (J6, J5) Two Altera Expansion Prototype Connectors (J23, J24, J25; J26, J27, J28)
TI-EVM/FPDP Connector (J31, J33)
The TI-EVM interface is specifically designed to work with TI boards that have the EVM interface. Refer to the Texas Instruments web site for details on which of their boards feature this connector. Table 2-35 lists the pin-outs for the TI-EVM and FPDP connectors.
Table 2-35. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 1 of 3) TI-EVM Signal Name J31
evm_DX0 evm_DR0 evm_IAK evm_INUM0 evm_CNTL0 evm_STAT0 evm_DMAC0 evm_CLKOUT2 evm_CLKX0 evm_FSX0 evm_CLKR0 evm_FSR0 evm_RESET evm_INT0 evm_INT1 evm_INT2 evm_INT3 J21 H22 K12 H13 L12 J12 H12 K11 J22 G22 K22 K21 J11 H11 L14 C13 B13
Stratix II Pin
J33
evm_A2 evm_A3 B20 E19
Altera Corporation
Core Version a.b.c variable 2-41 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Table 2-35. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 2 of 3) TI-EVM Signal Name
evm_A4 evm_A5 evm_A6 evm_A7 evm_A8 evm_A9 evm_A10 evm_A11 evm_A12 evm_A13 evm_A14 evm_A15 evm_A16 evm_A17 evm_A18 evm_A19 evm_A20 evm_A21 evm_D0 evm_D1 evm_D2 evm_D3 evm_D4 evm_D5 evm_D6 evm_D7 evm_D8 evm_D9 evm_D10 evm_D11 evm_D12 evm_D13 evm_D14
Stratix II Pin
C20 E20 A21 C21 A22 C22 D23 D21 F22 F23 A23 C23 C24 A24 A25 A26 D26 C26 E24 C25 E27 E26 A27 A28 D27 C27 B29 A29 D28 E28 D19 B21 D22
2-42 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Table 2-35. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 3 of 3) TI-EVM Signal Name
evm_D15 evm_D16 evm_D17 evm_D18 evm_D19 evm_D20 evm_D21 evm_D22 evm_D23 evm_D24 evm_D25 evm_D26 evm_D27 evm_D28 evm_D29 evm_D30 evm_D31 evm_BE_n0 evm_BE_n1 evm_BE_n2 evm_BE_n3 evm_AWE_n evm_ARDY evm_ACE2_n evm_ARE_n evm_AOE_n evm_ACE3_n
Stratix II Pin
B23 B25 D25 B27 C28 D20 B22 E22 B24 B26 E25 B28 C29 L21 G21 L18 J19 H20 L19 K19 G20 L20 H21 J20 K20 K18 E14
RS-232C Serial I/O Interface
The board contains a DB9 connector (J29), which provides a bidirectional RS-232C serial I/O interface. The board contains the transceiver (U41), however the logic controller (UART) must be implemented in the Stratix II device. Table 2-37 describes the device used to implement the RS-232C interface.
Altera Corporation
Core Version a.b.c variable 2-43 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
J29 is a standard DB-9 serial connector. This connector is typically used for communication with a host computer using a standard 9-pin serial cable connected to (for example) a COM port. Level-shifting buffers (U52 and U58) are used between J29 and the Stratix II device, because the Stratix II device cannot interface to RS-232 voltage levels directly. J29 is able to transmit all RS-232 signals. The Stratix II design may use only the signals it needs, such as J29's RXD and TXD. LEDs are connected to the RXD and TXD signals, giving a visual indication when data is being transmitted or received. Figure 2-9 shows the pin connections between the serial connector and the Stratix II device. Figure 2-9. Serial Connector J29
Function Direction Stratix II Pin # Connector Pin #
GND DTR1 RXD1 TXD1 DCD1 IN IN OUT OUT K13 L16 L17 H14 5 4 3 2 1
J19
Connector Pin # StratixII Pin # Direction Function
7 6 9 8 K17 K15 L15 K16 OUT OUT IN OUT RI1 CTS1 RTS1 DSR1
Table 2-36 shows the pin-outs for the RS-232C interface.
Table 2-36. RS-232C Serial Interface PinOuts Signal
TXD RXD DTR DCD DSR RI CTS RTS
Stratix II Pin
L17 L16 K13 H14 K16 K17 K15 L15
2-44 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Table 2-37 lists reference information for the RS-232C transciever device.
Table 2-37. RS-232C Interface Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer web site
Description
U41 MAX221E RS-232 transceiver 3.3 V Maxim www.maxim-ic.com
Analog Devices Corporation External A/D Support
The Stratix II EP2S180 DSP development board supports Analog Devices A/D converters via two 40-pin 0.1-inch digital I/O headers (J5, J6). These two dual-purpose digital I/O headers can support a maximum of the following three converters.

Two AD9433 converters Two AD6645 converters One AD9430 converter
Table 2-38 lists the pin-outs for the ADI connectors.
Table 2-38. ADI Connector (J5, J6) Pin-Outs (Part 1 of 2) ADI Signal Name
Adi_D0 Adi_D1 Adi_D2 Adi_D3 Adi_D4 Adi_D5 Adi_D6 Adi_D7 Adi_D8 Adi_D9 Adi_D10
Stratix II Pin
L3 L4 N4 N5 M3 M4 L1 L2 N2 N3 M1
Altera Corporation
Core Version a.b.c variable 2-45 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Table 2-38. ADI Connector (J5, J6) Pin-Outs (Part 2 of 2) ADI Signal Name
Adi_D11 Adi_D12 Adi_D13 Adi_D14 Adi_D15 Adi_D16 Adi_D17 Adi_D18 Adi_D19 Adi_D20 Adi_D21 Adi_D22 Adi_D23 Adi_D24 Adi_D25 Adi_D26 Adi_D27 Adi_D28 Adi_D29 Adi_D30 Adi_D31 Adi_D32 Adi_D33
Stratix II Pin
M2 R2 R3 P1 P2 J6 J7 J8 J9 K8 K9 L9 L10 L7 L8 K6 K7 L5 L6 M10 M11 M8 M9
2-46 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Expansion Prototype Connector (J23, J24, J25)
Headers J23, J24, and J25 collectively form a standard-footprint, mechanically stable connection that can be used (for example) as an interface to a special function daughter card.
f
For a list of available expansion daughter cards that can be used with the Stratix II EP2S180 DSP development board refer to www.altera.com/devkits. The expansion prototype connector interfaces include:

41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U19, U20, U21, U22 and U25) to protect the Stratix II device from 5 V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V. A buffered, zero-skew copy of the on-board OSC output from U2. A buffered, zero-skew copy of the Stratix II device's phase-locked loop (PLL)-output from U60. A logic-negative power-on reset signal. Five regulated 3.3-V power-supply pins (2 A total maximum load for both connectors. One regulated 5-V power-supply pin (1 A total maximum load for both connectors. Numerous ground connections.
Figures 2-10 and 2-11 show connections from the expansion prototype connector to the Stratix II device. Unless otherwise noted, labels indicate Stratix II device pin numbers. Figure 2-10. Expansion Prototype Connector - J23, J24, J25
J23
Pin 1
J25 J24
Pin 1 Pin 1
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Core Version a.b.c variable 2-47 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Figure 2-11. Expansion Prototype Connector Pin Information - J23, J24, J25
J24
GND M24 H30 G30 F30 1 3 5 7 9 2 4 6 8 10 12 14 VCC5 E31 H29 G29 F29 E29 D31
RESET_n R31 P32 M32 N31
1 3 5 7 9
2 4 6 8
GND R30 P31 M31
E30 11 D32 13
10 N30 12 L31 14 M29 16 N28 18 L29
L32 11 M30 13 N29 15 L30 17 GND 19
J23
20 NC 22 GND 24 GND 26 GND 28 J32 30 GND 32 H31 34 NC 36 F32 38 L26 40 GND
(1) Vunreg (U54 pin 2)
NC +3.3V +3.3V
1 3 5 7 9
2 4 6 8
GND GND GND GND
K32 21 K31 23 K30 25 K29 27 J31 29 H32 31 G32 33 G31 35 F31 37 E32 39
J25
(2) PROTO1_OSC (U2 pin 6)
10 GND 12 GND 14 GND 16 GND 18 GND 20 GND
(3) PROTO1_CLKIN (U2 pin 17) 11 (4) PROTO1_CLKOUT (AC14) 13
+3.3V 15 +3.3V 17 +3.3V 19
Notes to Figure 2-11:
(1) (2) (3) (4) Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from the card to the Stratix II device
2-48 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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Board Components & Interfaces
Expansion Prototype Connector (J26, J27, J28)
Headers J26, J27, and J28 collectively form a standard-footprint, mechanically-stable connection that can be used (for example) as an interface to a special-function daughter card. The expansion prototype connector interface includes:

41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U27, U28, U29, U30 and U31) to protect the Stratix II device from 5-V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V. A buffered, zero-skew copy of the on-board OSC output (from U2). A buffered, zero-skew copy of the Stratix II device's phase-locked loop (PLL)-output (from U60). A logic-negative, power-on reset signal. Five regulated 3.3-V power-supply pins (2A total max load for both expansion prototype connectors). One regulated 5-V power-supply pin (1A total max load for both expansion prototype connectors). Numerous ground connections.
Figures 2-12 and 2-13 show connections from the expansion prototype to the Stratix II device. Unless otherwise noted, the labels indicate Stratix II device pin numbers. Figure 2-12. Expansion Prototype Connector - J26, J27, J28
J27
Pin 1
J28 J26
Pin 1 Pin 1
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Core Version a.b.c variable 2-49 Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Figure 2-13. Expansion Prototype Connector -Pin Information for J26, J27, & J28
J26
GND AJ17 K26 L23 J26 1 3 5 7 9 2 4 6 8 10 12 14 +V5 K27 L24 J27 H28 K25 AK17
RESET_n AC27 AD27 Y23 Y25
1 3 5 7 9
2 4 6 8
GND AC26 AD26 Y22
H27 11 K24 13
10 Y24 12 AA26 14 Y26 16 W24 18 W26
AA27 11 Y27 13 W25 15 W27 17 GND 19
J27
20 NC 22 GND 24 GND 26 GND 28 V29 30 GND 32 U27 34 NC 36 L25 38 AF19 40 GND
J28
(1) Vunreg (U54 pin 2)
NC +3.3V +3.3V
1 3 5 7 9
2 4 6 8
GND GND GND GND
W29 21 W28 23 V24 25 V23 27 V28 29 U28 31 U23 33 U22 35 M23 37 M22 39
(2) PROTO2_OSC(U2 pin 6)
10 GND 12 GND 14 GND 16 GND 18 GND 20 GND
(3) PROTO2_CLKIN (U2 pin 17) 11 (4) PROTO2_CLKOUT (B14) 13
+3.3V 15 +3.3V 17 +3.3V 19
Notes to Figure 2-13:
(1) (2) (3) (4) Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from card connected to the Stratix II device.
2-50 Core Version a.b.c variable Stratix II EP2S180 DSP Development Board Reference Manual
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